module Mem:sig
..end
Note. All multi-bytes memory accesses are done in little endian
order.
typeaddr =
nativeint
val (+) : addr -> addr -> addr
a + off
adds off
to a
.val (-) : addr -> addr -> addr
a - off
subracts off
to a
.val offset : addr -> int -> addr
offset addr n
is add + Nativeint.of_int n
.val of_int32 : int32 -> addr
of_int32 i
is the address corresponding to i
.val pp_addr : Format.formatter -> addr -> unit
pp_addr ppf a
prints and unspecified reprsentation of a
on ppf
.val wait : int -> unit
wait n
waits at least n
CPU cycles.val dsb : unit -> unit
dsb ()
performs a data synchronization barrier. Returns when
all instructions before the call are complete.val dmb : unit -> unit
dmb ()
performs a data memory barrier. Ensures that all explicit
memory access before the call complete before any new explicit
access made after the call.val isb : unit -> unit
isb ()
performs an instruction synchronization barrier. Flushes
the pipeline in the processor so that all instruction following the
call are fetched from cache or memory.val get : addr -> int
get a
gets the byte at address a
.val get_int : addr -> int
get_int a
gets the 4 bytes starting at address a
.
Warning. Truncates the value of the 32nd bit.
val get_int32 : addr -> int32
get_int32 a
gets the 4 bytes starting at address a
.val get_int64 : addr -> int64
get_int64 a
gets the 8 bytes starting at address a
.val set : addr -> int -> unit
set a v
sets the byte at address a
to v
.val set_int : addr -> int -> unit
set a v
sets the 4 bytes starting at address a
to v
.val set_int32 : addr -> int32 -> unit
set a v
sets the 4 bytes starting at address a
to v
.val set_int64 : addr -> int64 -> unit
set a v
sets the 8 bytes starting at address a
to v
.val set_bits : addr -> bits:int -> int -> unit
val set_int_bits : addr -> bits:int -> int -> unit
val set_int32_bits : addr -> bits:int32 -> int32 -> unit
val set_int64_bits : addr -> bits:int64 -> int64 -> unit
module Map:sig
..end